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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt82d20 single channel e1 line interface unit august 2006 rev. 1.0.8 general description the xrt82d20 is a fully integrated, single channel, line interface unit (transceiver) for 75 ? or 120 ? e1 (2.048 mbps) applications. the liu consists of a receiver with adaptive data slicer for accurate data and clock recovery and a transmitter which accepts either single or dual-rail digital inputs for signal transmission to the line using a low- impedance differential line driver. the liu also includes a crystal- less jitter attenuator for clock and data smoothing which, depending on system requirements, can be selected in either the transmit or receive path. coupling the xrt82d20 to the line requires transformers on both the receiver and transmitter sides, and supports both 120 ? balanced and 75 ? unbalanced interfaces. the receiver can be capacitive coupled to for cost reduction features ? complete e1 (cept) line interface unit ? generates transmit out put pulses that are compliant with the itu-t g. 703 pulse template for 2.048mbps (e1) rates ? on-chip pulse shaping for both 75 ? and 120 ? line drivers ? clock recovery and select able crystal-less jitter attenuator ? compliant with ets300166 return loss ? compliant with the itu-t g.823 jitter tolerance requirements ? remote, local and digital loop backs ? declares and clears los per itu-t g.775 ? logic inputs accept either 3.3v or 5.0v levels ? - 40 0 c to 85 0 c temperature range ? low power dissipation; 145mw with 120 ? or 160mw with 75 ? typical ? +3.3v or +5v su pply operation ? pin compatible with the xrt7288 applications ? pdh multiplexers ? sdh multiplexers ? digital cross-connect systems ? dect (digital european cordless telephone) base stations ? csu/dsu equipment ? test equipment f igure 1. b lock d iagram of the xrt82d20 hdb3 encoder peak detector local loopback los detect data slicer data & timing recovery remote loopback hdb3 decoder digital loopback tx pulse shaper mux mux line driver tclk tpos tneg rclk rpos rneg ttip tring rlos rtip rring mclk timing generator jitter attenuator
xrt82d20 2 single channel e1 line interface unit rev. 1.0.8 ordering information f igure 2. p inout of the xrt82d20 p art # p ackage o perating t emperature r ange xrt82d20iw 28 lead 300 mil jedec soj -40 o c to + 85 o c rlos clklos tneg/code rneg/lcv rclk rpos/rdata tclk tpos/tdata lloop rloop dloop atm raos taos rtip rring muterx agnd avdd txlev ttip tvdd tring tgnd jaen digi jatx/rx mclk 1 2 9 13 12 11 10 8 7 6 5 4 3 14 28 27 20 16 17 18 19 21 22 23 24 25 26 15
xrt82d20 i rev. 1.0.8 single channel e1 line interface unit table of contents general description........ ................. ................ ................ ............... .............. .......... 1 features....................................................................................................................... .......................... 1 applications........... ................. ................ ................ ................ ............. ............. ............. ....................... 1 f igure 1. b lock d iagram of the xrt82d20...................................................................................................................... ......... 1 f igure 2. p inout of the xrt82d20...................................................................................................................... ....................... 2 o rdering i nformation .............................................................................................................................. 2 t able of contents ................. ................ ................. ................ ................. .............. ........... i pin descriptions ............. ................ ................ ................. ................ ................. .......... 3 f igure 3. i nterface t iming d iagram in b oth s ingle -r ail and d ual -r ail m ode , with digi (p in 17) = ?0? ............................... 6 f igure 4. i nterface t iming d iagram in d ual -r ail m ode only , with digi (p in 17) = ?1? ........................................................... 6 electrical characteristics .............. .............. .............. ............... .............. .......... 7 t able 1: r eceiver c haracteristics .............................................................................................................................. .............. 7 t able 2: t ransmitter c haracteristics .............................................................................................................................. ......... 7 t able 3: 3.3v p ower c onsumption including l ine p ower d issipation , t ransmission and r eceive p aths all a ctive .......... 7 t able 4: 5v p ower c onsumption including l ine p ower d issipation , t ransmission and r eceive p aths all a ctive ............. 8 t able 5: ac e lectrical c haracteristics .............................................................................................................................. .... 8 t able 6: dc e lectrical c haracteristics .............................................................................................................................. ..... 9 a bsolute maximum r atings .............................................................................................................. 9 f igure 5. r eceiver m aximum j itter t olerance , t est c onditions : t est p attern 215-1, (-6 d b) c able l oss ....................... 10 f igure 6. r eceiver j itter t ransfer f unction (j itter a ttenuator d isabled ), t est c onditions : t est p attern 215-1, i nput j it - ter 0.5ui p - p ............................................................................................................................... ................................. 10 f igure 7. r eceiver j itter t ransfer f unction (j itter a ttenuator enabled ) t est c onditions : t est p attern 215-1, i nput j itter 75% of m aximum j itter t olerance ........................................................................................................................... 11 system description......... ................ ................. ................ .............. .............. ........... 12 1.0 the receive section........................................................................................................ ............... 12 1.1 jitter attenuator .......................................................................................................... ........................... 12 1.2 the transmit section....................................................................................................... ......................... 12 f igure 8. i llustration on how the xrt82d20 s amples the data on the tpos and tneg input pins ................................ 13 1.3 the pulse shaping circuit ......... .............. .............. .............. .............. ........... ........... ........... .................... 13 f igure 9. i llustration of the itu-t g.703 p ulse t emplate for e1 a pplication .................................................................. 14 1.4 interfacing the transmit section of the xrt82d20 to the line.... .............. ............ ........... ..... 15 f igure 10. i llustration of how to interface the xrt82d20 to the l ine for 75 o hm a pplications and 3.3v operation only 15 f igure 11. i llustration of how to interface the xrt82d20 to the l ine for 120 o hm a pplications and 3.3v operation only 16 1.5 interfacing the receive section to the line................................................................................ .. 17 f igure 12. r ecommended s chematic for t ransformer -c oupling the xrt82d20 to the l ine for 75 o hm a pplications and 5 v operation only ............................................................................................................................... ........................ 17 f igure 13. r ecommended s chematic for t ransformer -c oupling the xrt82d20 to the l ine for 120 o hm a pplications and 5 v operation only ............................................................................................................................... ........................ 18 1.6 capacitively-coupling the receive section(s) of the xrt82d20 to the line...................... 19 f igure 14. c apacitively - coupling the r eceive s ection for 75 o hm a pplication and 3.3v supply ..................................... 19 f igure 15. c apacitively - coupling the r eceive s ection for 120 o hm a pplication and 3.3v supply ................................... 20 f igure 16. c apacitively - coupling the r eceive s ection for 75 o hm a pplication and 5v supply ........................................ 21 f igure 17. c apacitively - coupling the r eceive s ection for 120 o hm a pplication and 5v supply ...................................... 22 2.0 diagnostic features........................................................................................................ ............. 23 2.1 the local loop-back mode .......... .............. .............. .............. .............. ........... ........... ........... ................. 23 f igure 18. i llustration of the a nalog l ocal l oop -b ack within the xrt82d20 .................................................................. 23 2.2 the remote loop back mode........ .............. .............. .............. .............. ........... ........... ............ ................ 24 f igure 19. i llustration of the r emote l oop -b ack path , within the xrt82d20................................................................... 24 package outline drawi ng................... .............. .............. ............... .............. ........ 25 r evision h istory ............................................................................................................................... ...... 26
xrt82d20 3 single channel e1 line interface unit rev. 1.0.8 pin descriptions p in # s ymbol t ype d escription 1 rlos o receiver loss of signal: this pin toggles low to indicate the loss of signal at the receive inputs. 2 clklos o receiver loss of clock : with muterx=1, this pin will toggle low to indicate a loss of clock has occurred when the receive signal is lost (rlos=0). when rlos=0, no transitions occur on rclk, rpos/rdata and rneg outputs. 3 tneg/ code i transmitter negative data input/coding select : with jitter attenuator enabled (pin 18=1), input activity on this pin det ermines whether the device is configured to operate in single-rail or dual-rail mode. with n-rail transmit data applied to this pin, the device is automatically configured to o perate in dual-rail mode for both transmit input and receive output. if this pin is tied high for more than 16 clock cycles, the device is configured to oper - ate in single-rail mode with hdb3 encoding and decoding functions enabled. if this pin is tied low for more than 16 clock cycles, the device is configured to oper - ate in single-rail mode with ami encoding and decoding functions enabled. (internal pull-down). 4 rneg/lcv o receive negative data/line code violation output: if the device is configured in dual-rail mode with n-rail data applied to pin 3, then the receive negative data will be output through this pin. if the device is configured in sing le-rail mode and operate with hdb3 coding enabled, hdb3 code violation will be detected and cause this pin to go high. if the device is configured in single-rail mode and with ami coding selected, every bipolar violation will be reported at this pin. 5 rclk o receive clock: output receive clock signal to the terminal equipment. 6 rpos/ rdata o receive positive/ data output: in dual-rail mode, this signal is the p-rail receive output data. in single-rail mode, this signal is the receive output data. 7 tclk i transmitter clock input: input clock signal (2.048 mhz 50ppm) 8 tpos/ tdata i transmit positive / data input: in dual-rail mode, this signal is the p-rail transmit input data. in single-rail mode, this signal is the transmit input data. 9 lloop i local loop back enable (active low): tie this pin low to enable analog local loop-back.in local loop-back mode, transmit output data is looped back to the input of the receiver.input signal at rtip and rring are ignored. local loop-back has priority over remote and digital loop- back mode. see ?section 2.2, the remote loop back mode? on page 24 for more details. (internal pull-up). 10 rloop i remote loop back enable (active low): connect this pin to ground to enable remote loop-back. in remote loop-back mode, transmit data at tpos/tda ta and tneg are ignored. see ?section 2.2, the remote loop back mode? on page 24 for more details. (internal pull- up).
xrt82d20 4 rev. 1.0.8 single channel e1 line interface unit 11 dloop i digital loop back enable (active low): connect this pin to ground to enable digital local loop-back.in digital loop-back mode, transmit input data after the encoder is looped back to the jitter attenuator (if selected) and to the receive decoder. input data at rtip and rring are ignored in this mode. (internal pull-up). in this mode, the xrt82d20 can operate only as a jit - ter attenuator. 12 atm i alarm test mode (active-low): connect this pin to ground to force clklos, rlos = 0 and lcv = 1 for testing with - out affecting data transmission. (internal pull-up) 13 raos i receive all ones: with this pin tied to high, an all ?1?s? signal is inserted to the receiver output at rpos and rneg/rdata using mclk as timing reference. this control has priority over digital loop-back if both are enabled. (internal pull-down). 14 taos i transmit all ones: with this pin tied high, an ami encoded all ?1?s? signal is sent to the transmit output using mclk as timing reference. this control has priority over remote loop-back if both are enabled. (internal pull-down). 15 mclk i master clock input: this signal is an independent 2.048 mhz clock with accuracy better than + 50 ppm and duty cycle within 40% to 60%. the function of mclk is to provide timing source for the pll clock recovery circuit, reference cl ock to insert all ?1?s ? data in the trans - mit as well as receive paths. this signal must be available for the device to operate. 16 jatx/ rx (dr/ sr) i jitter attenuator path select: with the jitter attenuator enabled, (pin 18 =? 1?), tie this pin ?high? to select the jitter attenuator in the transmit pa th and tie it ?low? to select in the receive path. data input/output format is then controlled automat ically by the status of the tneg input. if tneg data is present the device operates in dual-rail data mode. dual-rail/single -rail select: with the jitter attenuator disa bled, (pin 18 =?0?), tie this pin ?high? to select dual-rail data format and tie it ?low? to select sing le-rail data format. (internal pull-down) 17 digi i digital interface: with this pin tied low, input data at tpos/tdata and tneg/code is active-high and will be sampled by tclk on the falling edge, while active-high rpos/rdata and rneg output data are updated on the falling edge of rclk. see figure 3 and 4 for details. with his pin tied high and in dual-rail mode, transmit input accepts active-low tpos/tdata and tneg/code data and will be sampled by tclk on the falling edge, while rpos/rdata and rneg/lcv ar e active-low, data is updated on the rising edge of rclk. (internal pull-down). 18 jaen i jitter attenuator enable (active high): connect this pin high to enable the jitter attenuation function. ji tter attenuator path select is determined by the pin 16 setting. (internal pull-down) 19 tgnd - transmitter supply ground 20 tring o transmitter ring output: negative bipolar data output to the line. 21 tvdd - transmit positive supply: 5.0 v + 5% or 3.3 v + 5% p in #s ymbol t ype d escription
xrt82d20 5 single channel e1 line interface unit rev. 1.0.8 22 ttip o transmitter tip output: positive bipolar data output to the line. 23 txlev i transmit level: tie this pin high for 120 ? twisted pair cable operation and tie it low for 75 ? coaxial cable operation (internal pull-down). this pin is only active for 5.0v operation. 24 avdd - analog positive supply 5.0 v + 5% or 3.3 v + 5% 25 agnd - analog supply ground 26 muterx i mute receive output: with this pin tied high, a loss of receive input signal (rlos=0) will cause clklos to go low and generate the following. dual-rail mode operation: with digi = 0, rclk = 1, rpos and rneg/rdata = 0 fwith digi = 1, rclk =0, rpos and rneg/rdata = 1 single-rail mode: rclk = 1 and rdata=0 (internal pull-down) 27 rring i receive bipolar negative input: bipolar line signal input to the receiver. 28 rtip i receiver bipolar positive input: bipolar line signal input to the receiver. p in #s ymbol t ype d escription
xrt82d20 6 rev. 1.0.8 single channel e1 line interface unit f igure 3. i nterface t iming d iagram in b oth s ingle -r ail and d ual -r ail m ode , with digi (p in 17) = ?0? f igure 4. i nterface t iming d iagram in d ual -r ail m ode only , with digi (p in 17) = ?1? tclk tpos/tdata or tneg/code active high active high rclk rpos/rdata or rneg/lcv tclk t r t f t r t f t rcd t rsu t rho t tho t tsu tclk tpos/tdata active low active low rclk rpos/rdata t r t f tclk t tsu t tho t r t f t rsu t rho t rcd
xrt82d20 7 single channel e1 line interface unit rev. 1.0.8 electrical characteristics t able 1: r eceiver c haracteristics ta = 25c, vdd = 3.3v 5% or 5v 5% unless otherwise specified p arameter m in . t yp . m ax u nit receiver sensitivity 0.7 4.2 vp interference margin with -6db cable loss -18 -14 - db input impedance measured between rtip or rring to ground 0.9 2.0 - k ? recovered clock jitter transfer corner frequency peaking amplitude - - 18 0.1 36 0.5 khz db jitter attenuator corner frequency (-3db curve) - 20 40 hz return loss 51khz-102khz 102khz-2048khz 2048khz-3072khz 12 18 14 25 35 25 - - - db db db t able 2: t ransmitter c haracteristics ta = 25c, vdd = 3.3v 5% or 5v 5% unless otherwise specified p arameter m in . t yp . m ax u nit ami output pulse amplitude 75 ? application 120 ? application 2.14 2.70 2.37 3.00 2.60 3.30 v v output pulse width 224 244 264 ns output pulse amplitude ratio 0.9 1.0 1.1 jitter added by the transmitter output - 0.025 0.050 uipp output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz - - - 20 25 20 - - - db db db t able 3: 3.3v p ower c onsumption including l ine p ower d issipation , t ransmission and r eceive p aths all a ctive ta = -40 to 85c, vdd = 3.3v 5% unless otherwise specified s ymbo l p arameter m in . t yp . m ax u nit c onditions pc power consumption - 100 140 mw 75 ? load, operating at 50% mark density pc power consumption - 92 130 mw 120 ? load, operating at 50% mark density pc power consumption - 150 190 mw 75 ? load, operating at 100% mark density
xrt82d20 8 rev. 1.0.8 single channel e1 line interface unit pc power consumption - 125 160 mw 120 ? load, operating at 100% mark den - sity t able 4: 5v p ower c onsumption including l ine p ower d issipation , t ransmission and r eceive p aths all a ctive (ta = -40 to 85c, vdd = 5v 5% unless otherwise specified) s ymbo l p arameter m in . t yp . m ax u nit c onditions pc power consumption - 160 210 mw 75 ? load, operating at 50% mark density pc power consumption - 145 195 mw 120 ? load, operating at 50% mark density pc power consumption - 200 260 mw 75 ? load, operating at 100% mark density pc power consumption - 180 240 mw 120 ? load, operating at 100% mark den - sity t able 5: ac e lectrical c haracteristics ta = -40 to +85 c, vdd = 3.3v 5% or 5v 5% unless otherwise specified p arameter s ymbol m in . t yp m ax u nits clock frequency mclk -50 ppm 2.048 +50ppm mhz clock duty cycle mclk 40 50 60 % clock period tclk - 244 - ns tclk duty cycle tcdu 30 50 70 % transmit data setup time t tsu 40 - - ns transmit data hold time ttho 40 - - ns tclk rise time (10% /90%) tr - - 40 ns tclk fall time (90% / 10%) tf - - 40 ns rclk duty cycle rcdu 45 50 55 % receive data setup time t rsu 150 244 - ns receive data hold time t rho 150 244 - ns rclk to data delay t rcd - - 40 ns rclk rise time (10%/90%) t r - - 40 ns rclk fall time (90%/10%) t f - - 40 ns t able 3: 3.3v p ower c onsumption including l ine p ower d issipation , t ransmission and r eceive p aths all a ctive ta = -40 to 85c, vdd = 3.3v 5% unless otherwise specified s ymbo l p arameter m in .t yp .m ax u nit c onditions
xrt82d20 9 single channel e1 line interface unit rev. 1.0.8 n ote : all digital output pins except pin 1 and pin 2, whic h typically source 20a at voh and sink -4ma at vol t able 6: dc e lectrical c haracteristics ta = 25c, vdd=3.3v 5% or 5v 5% unless otherwise specified p arameter s ymbol m in t yp m ax u nit input high voltage v ih 2.0 3.3 or 5.0 5.5 v input low voltage v il 0.5 0 0.8 v output high voltage @ioh=5ma (see note) vdd=3.3v vdd=5.0v v oh 2.4 2.4 - vdd vdd v output low voltage @ iol=5ma (see note) vdd=3.3v vdd=5.0v v ol 0 0 - 0.4 0.4 v input leakage current (except input pins with pull-up resistors) i l - 0 10 ua input capacitance c i - 5 20 pf output load capacitance c o - - 20 pf absolute maximum ratings storage temperature -65 to 150c operating temperature -40 to 85c supply voltage -0.5v to +5.5v
xrt82d20 10 rev. 1.0.8 single channel e1 line interface unit f igure 5. r eceiver m aximum j itter t olerance , t est c onditions : t est p attern 2 15 -1, (-6 db) c able l oss f igure 6. r eceiver j itter t ransfer f unction (j itter a ttenuator d isabled ), t est c onditions : t est p at - tern 2 15 -1, i nput j itter 0.5ui p - p 10 0 10 1 10 2 10 3 10 4 10 5 10 ?1 10 0 10 1 10 2 10 3 (freq.(mhz)) input jitter (uip?p) jat disabled itu-t g.823 mask jat enabled 10 2 10 3 10 4 1 0 5 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 (freq.(mhz)) 20log(jout/jin) (db) t82d20 performance g.735-g739 specification
xrt82d20 11 single channel e1 line interface unit rev. 1.0.8 f igure 7. r eceiver j itter t ransfer f unction (j itter a ttenuator enabled ) t est c onditions : t est p at - tern 2 15 -1, i nput j itter 75% of m aximum j itter t olerance 10 0 10 1 10 2 10 3 10 4 1 0 5 ?60 ?50 ?40 ?30 ?20 ?10 0 10 (freq.(mhz)) jitter attenuation (db) t82d20 performance itu.g.736 mask
xrt82d20 12 rev. 1.0.8 single channel e1 line interface unit system description the xrt82d20 is a single channel e1 transceiver t hat provides an electrical interface for 2.048mbps applications. xrt82d20 includes a re ceive circuit that converts an itu-t g.703 compliant bipolar signal into a ttl compatible logic levels. the receiver also includes an los (loss of signal) detection circuit. similarly, in the transmit direction, the transmitter converts ttl comp atible logic levels into a g.703 compatible bipolar signal. the xrt82d20 consists of both a receive section, ji tter attenuator and transmit section; each of these sections will be discussed below. 1.0 the receive section at the receiver input, cable attenuated ami signal can be coupled to the receiver using a capacitor or transformer. the receive data first goes through th e peak detector and data slicer for accurate data recovery.the digital representation of the ami signals go to the clock recovery circuit for timing recovery and subsequently to the decoder (if selected) for hdb3 decoding before being output to the rpos/rdata and rneg/lcv pins. the digital data output can be in nrz or rz format depending the mode of operation selected and with the option to be in dual-rail or single rail mode. clock timing recove ry of the line interface is accomplished by means of a digital pll sc heme which has high input jitter tolerance. the purpose of the receive output interface block is to interface directly with the receiving terminal equipment. the receive output interface block outp uts the data (which has been recovered from the incoming line signal) to the re ceive terminal equipment via the rpos and rneg output pins. if the receive section of the xrt82d20 has received a positive-polarity pulse, via the rtip and rring input pins, then the receive output interface will output a pulse at the rpos output pin. similarly, if the receive section of the xrt82d20 has received a negative-polarity pulse, via the rtip and rring input pins, then the receive output interface will output a pu lse at the rneg output pin. 1.1 jitter attenuator to reduce frequency jitter in the transmit clock or rece ive clock, a crystal-less jitter attenuator is provided. the jitter attenuator can be selected either in the transmit or receive path or it can be disabled. 1.2 the transmit section in general, the purpose of the transmit section (withi n the xrt82d20) is to accept ttl/cmos level digital data (from the terminal equipment), and to encode it into a format such that it can: 1. be efficiently transmitted over coaxial- or twisted pair cable at the e1 data rate; and 2. be reliably received by the remote terminal equipment at the other end of the e1 data link. 3. comply with the itu-t g.703 pulse temp late requirements, for e1 applications a 2.048 mhz clock is applied to the tclk input pin an d nrz data at the tpos and tneg input pins. the transmit input inte rface circuit will sample the data, at the tpos and tneg input pins, upon the falling edge of tclk, as illustrated in figure 8 below.
xrt82d20 13 single channel e1 line interface unit rev. 1.0.8 in general, if the xrt82d20 samples a ?1? on the tpos input pi n, then the transmit section will ultimately generate a positive polarity pulse via the ttip and tring output pins (across a 1:2 tr ansformer). conversely, if the xrt82d20 samples a ?1? on the tneg input pin, then the transmit section of the device will ultimately generate a negative polarity pulse via the ttip and tring output pins (across a 1:2 transformer). 1.3 the pulse shaping circuit the purpose of the transmit pulse shap ing circuit is to generate transmit output pulses that comply with the itu-t g.703 pulse template requi rements for e1 applications. an illustration of the itu-t g.703 pulse temp late requirements is presented below in figure 9 . with input signal as descr ibed above, the xr t82d20 will take each mark (which is provided to it via the transmit input interface block, an d will generate a puls e that complies with the puls e template, presented in figure 9 (when measured on the secondary side of the transmit output transformer). f igure 8. i llustration on how the xrt82d20 s amples the data on the tpos and tneg input pins tclk tpos tneg tsu tho
xrt82d20 14 rev. 1.0.8 single channel e1 line interface unit f igure 9. i llustration of the itu-t g.703 p ulse t emplate for e1 a pplication 10% 10% 10% 10% 10% 10% 269 ns (244 + 25) 194 ns (244?50) 244 ns 219 ns (244 ? 25) 488 ns (244 + 244) 0% 50% 20% v = 100% nominal pulse note ? v corresponds to the nominal peak value. 20% 20%
xrt82d20 15 single channel e1 line interface unit rev. 1.0.8 1.4 interfacing the transmit section of the xrt82d20 to the line itu-t g.703 specifies that the e1 line signal can be tr ansmitted over coaxial cable and terminated with 75 ? or transmitted over twisted-pair and terminated with 120 ? . in both applications (e.g., 75 ? or 120 ? , the user is advised to interface the transmitter to the line, in the manner as depicted in figure 10 and figure 11 , respectively. f igure 10. i llustration of how to interface the xrt82d20 to the l ine for 75 o hm a pplications and 3.3v operation only r load 75 ? 270 ? 270 ? 9.1 ? 9.1 ? 1 : 2 2 : 1 rtip rring ttip tring +3.3 v 0.1 f tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 f rxx input tx output 75 ? coax 75 ? coax 75 ? signal source
xrt82d20 16 rev. 1.0.8 single channel e1 line interface unit n otes : 1. figure 10 and figure 11 indicate that for 3.3 v operation, both 75 ? and 120 ? applications, the user should connect a 9.1 ? resistor in series between the ttip/tring outputs and the transformer. 2. figure 10 and figure 11 indicate that the user should use a 2 : 1 step-up transformer. f igure 11. i llustration of how to interface the xrt82d20 to the l ine for 120 o hm a pplications and 3.3v operation only 866 ? 866 ? r load 120 ? 9.1 ? 9.1 ? 1 : 2 2 : 1 rtip rring ttip tring +3.3 v 0.1 f tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 f 120 ? twisted pair 120 ? signal source 120 ? twisted pair rx input tx output
xrt82d20 17 single channel e1 line interface unit rev. 1.0.8 1.5 interfacing the receive section to the line the design of the xrt82d20 permits the user to trans former-couple the receive section to the line. as mentioned earlier, the specif ications for e1 require 75 ? termination loads, when transmitting over coaxial cable, and 120 ? loads, when transmitti ng over twisted-pair. figure 12 and figure 13 present the various methods that the user can employ to interfac e the receiver of the xrt82d20 to the line. f igure 12. r ecommended s chematic for t ransformer -c oupling the xrt82d20 to the l ine for 75 o hm a pplications and 5 v operation only 270 ? 270 ? 15.4 ? 15.4 ? 1 : 2 1.36 : 1 rtip rring ttip tring +5 v 0.11 f tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 f r load 75 ? 75 ? coax 75 ? coax 75 ? signal source rx input tx output
xrt82d20 18 rev. 1.0.8 single channel e1 line interface unit n ote : figure 12 and figure 13 indicate that the user should use a 1.36 :1 step-up transformer, when interfacing the receiver to the line. f igure 13. r ecommended s chematic for t ransformer -c oupling the xrt82d20 to the l ine for 120 o hm a pplications and 5 v operation only 866 ? 866 ? 26.1 ? 26.1 ? 1 : 2 1.36 : 1 rtip rring ttip tring +5 v 0.1 f tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 f r load 120 ? 120 ? twisted pair 120 ? signal source 120 ? twisted pair tx output rx input
xrt82d20 19 single channel e1 line interface unit rev. 1.0.8 1.6 capacitively-coupling the receive sect ion(s) of the xrt82d20 to the line capacitive coupling provides a lower cost interface to the line. it must be no ted that the line is olation is limited to the breakdown voltage of the capactior versus the typica l transformer isolation of 1, 500 to 3,000 volts. with a capacitor there is also no dc isolation to ground as there is with with a transformer. applications that are not se nsitive to these issues can benefit from the lower cost approach of using capacitor coupling on the receive input. see figure 14 , figure 15 , figure 16 and figure 17 for the recommended schematics for capacitively coupling the receiver to the line. n ote : resistive divider attenuates the input signal by one-half for both 75 ? and 120 ? applications. f igure 14. c apacitively - coupling the r eceive s ection for 75 o hm a pplication and 3.3v supply r load 75 ? 75 ? coax 75 ? coax 75 ? signal source 37.4 ? 37.4 ? 9.1 ? 9.1 ? 2:1 rtip rring ttip tring +3.3 v 0.1 f tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 f rx input tx output 0.1 f 0.1 f
xrt82d20 20 rev. 1.0.8 single channel e1 line interface unit n ote : resistive divider attenuates the input signal by one-half for both 75 ? and 120 ? applications. f igure 15. c apacitively - coupling the r eceive s ection for 120 o hm a pplication and 3.3v supply 30.1 ? 60.4 ? 9.1 ? 9.1 ? 2:1 rtip rring ttip tring +3.3 v 0.1 f tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 f rx input tx output 0.1 f 0.1 f 30.1 ? r load 120 ? 120 ? twisted pair 120 ? signal source 120 ? twisted pair
xrt82d20 21 single channel e1 line interface unit rev. 1.0.8 n ote : resistive divider attenuates the input signal by one-half for both 75 ? and 120 ? applications. f igure 16. c apacitively - coupling the r eceive s ection for 75 o hm a pplication and 5v supply r load 75 ? 75 ? coax 75 ? coax 75 ? signal source 37.4 ? 15.4 ? 15.4 ? 1.36:1 rtip rring ttip tring +5 v 0.1 f tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 f rx input tx output 0.1 f 0.1 f
xrt82d20 22 rev. 1.0.8 single channel e1 line interface unit n ote : resistive divider attenuates the input signal by one-half for both 75 ? and 120 ? applications. f igure 17. c apacitively - coupling the r eceive s ection for 120 o hm a pplication and 5v supply 30.1 ? 60.4 ? 26.1 ? 26.1 ? 1.36:1 rtip rring ttip tring +5 v 0.1 f tvdd avdd txlev tneg/code tpos/tdata tclk rpos/rdata rneg/lcv rclk agnd tgnd 10 f rx input tx output 0.1 f 0.1 f 30.1 ? r load 120 ? 120 ? twisted pair 120 ? signal source 120 ? twisted pair
xrt82d20 23 single channel e1 line interface unit rev. 1.0.8 2.0 diagnostic features in order to support diagnostic operations, the xrt82d20 supports the following loop-back modes: ? local loopback ? remote loopback ? digital loopback each of these loop-back mo des will be discussed below. 2.1 the local loop-back mode when the xrt82d20 is configured to operate in the local loop-back mode, the xrt82d20 will ignore any signals that are input to the rtip and rring input pins. the tran smitting terminal equi pment will transmit data into the xrt82d20 via the tpos , tneg and tclk input pins. this data will be processed through the transmit terminal input interface and the pulse shaping circuit. finally, th is data will be output to the line via the ttip and tring output pins. additionally, this data (which is being output via the ttip and tring output pins) will be looped back into the receiver block. as a consequence, this data will also be proc essed through the entire receive section of the xrt82d20. after this post-loop-back data has been processed through the receive section it will output , to the near-end receiving terminal eq uipment via the rpos and rneg output pins. figure 18 , illustrates the path that the data takes (within the xrt82d20), when the chip is configured to operate in the local loop-back mode. the user can configure the xrt82d20 to operate in the local loop-back mode, by pulling the lloop input pin (pin 9) to gnd. f igure 18. i llustration of the a nalog l ocal l oop -b ack within the xrt82d20 hdb3 encoder peak detector local loopback los detect data slicer data & timing recovery hdb3 decoder tx pulse shaper mux mux line driver tclk tpos tneg rclk rpos rneg ttip tring rlos rtip rring mclk timing generator jitter attenuator
xrt82d20 24 rev. 1.0.8 single channel e1 line interface unit 2.2 the remote loop back mode when the xrt82d20 is conf igured to operate in the remote loop-back mode, the xrt82d20 will ignore any signals that are input to the tpos and tneg input pins. the xrt82d20 will receive the incoming line signals, via the rtip and rring input pins. this data will be processed through the entir e receive section (within the xrt82d20) and will output to the receive terminal equipment via the rpos and rneg output pins. additionally, this data will also be internally looped back to the transmit input interface block within the transmit section. at this point, this data will be routed th rough the remainder of the transmit section of the xrt82d20 and will be transmitted out onto th e line via the ttip and tring output pins. figure 19 , illustrates the path that the data takes (within the xrt82d20) when the ch ip is configured to operate in the remote loop-back mode. n ote : during remote loop-back operation, any data which is i nput via the rtip and rring in put pins, will also be output to the terminal equipment, via the rpos and rneg output pins. f igure 19. i llustration of the r emote l oop -b ack path , within the xrt82d20 hdb3 encoder peak detector los detect data slicer data & timing recovery remote loopback hdb3 decoder tx pulse shaper mux mux line driver tclk tpos tneg rclk rpos rneg ttip tring rlos rtip rring mclk timing generator jitter attenuator
xrt82d20 25 single channel e1 line interface unit rev. 1.0.8 package outline drawing
26 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet august 2006. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xrt82d20 rev. 1.0.8 single channel e1 line interface unit revision history rev. 1.0.6 corrections to figures, remove values fr om pull-up/down resistors, correct formating of . rev. 1.0.7 minor edits of figures and text. added 4 new figures 14, 15, 16 and 17, showing capacitive coupling of the receiver to the line. rev. 1.0.8 edit pin 9 and 10 as internal pull-up. updated new format with new exar logo.

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